The present invention relates to semiconductor devices, particularly memory devices, and more particularly to a method and system for providing lines of similar size and, therefore, similar characteristics.
Currently, semiconductor memory devices are used for many applications. Semiconductor memory devices typically include memory cells in their core region. Flash memory cells typically include floating gates made of first polysilicon lines formed from a first layer of polysilicon, control gates made of polysilicon word lines formed from a second layer of polysilicon and an insulating layer that separates the control gates from the floating gates. The floating gates are typically separated from the semiconductor substrate by a gate dielectric layer. In addition, select gates are typically provided. The select gates are typically at each end of the word lines. For example, sixteen word lines are typically provided. Before the first word line and after the sixteenth word line, a select gate is provided.
FIG. 1 depicts a conventional method 10 for providing polysilicon lines, such as the word lines, in a memory device, such as a NAND memory device. A conventional mask for use in printing a conventional pattern on a layer of photoresist is provided, via step 12. The conventional mask has a single polygon, or line, for each word line and each select gate to be provided in the polysilicon layer. The select gates, which are adjacent to the word lines, are spaced farther from the first and last word lines than the word lines are spaced from each other.
A second layer of polysilicon for the word lines is provided on the conventional memory device, via step 14. A layer of photoresist is then spun on the second polysilicon layer, via step 16. A conventional pattern is then printed on the photoresist using the conventional mask, via step 18. Thus, a conventional physical mask is formed in step 18. The conventional physical mask covers portions of the second polysilicon layer which will become the word lines and the select gates. The underlying polysilicon layer is then etched, via step 20. Thus, the word lines are formed in step 20. The conventional physical mask is then stripped and conventional processing continues, via step 22.
FIG. 2A depicts a conventional mask 30 provided in step 12 of the conventional method 10. The conventional mask 30 includes polygons 32 and 36 for the select gates. The conventional mask 30 also includes polygons 34-1, 34-2, 34-3, 34-4, and 34-5 for the word lines in the conventional memory device. Although only polygons 34-1 through 34-5 for five lines are depicted, typically a larger number of lines, such as sixteen, are formed. Thus, polygons for sixteen lines are typically provided. The polygons 34-1, 34-2, 34-3, 34-4 and 34-5 are separated by the same spacing, s2, and have the same width, w2. The polygons 32 and 36 have the same width, w1, and are separated from adjacent polygons 34-1 and 34-5, respectively, by the spacing s1. Typically, the spacing si is greater than the spacing s2.
FIG. 2B depicts a portion of the conventional memory device 40 including the conventional physical mask 50 provided in step 18 of the conventional method 10. The conventional memory device 40 includes a substrate 41 and a polysilicon layer 42 that is to be etched to form the word lines and select gates. The conventional physical mask 50 includes conventional lines 52 and 56 corresponding to the select gates. The conventional physical mask 50 also includes conventional lines 54-1, 54-2, 54-3, 54-4 and 54-5 corresponding to the word lines.
FIG. 2C depicts the conventional semiconductor memory device 40xe2x80x2 after the polysilicon lines have been etched in step 22 and the conventional physical mask has been stripped in step 22 of the method 10 depicted in FIG. 1. Referring to FIG. 2C, the conventional memory device 40xe2x80x2 still includes the substrate 41xe2x80x2. However, the polysilicon layer 42 has been etched to form select gates 62 and 66 and word lines 64-1, 64-2, 64-3, 64-4 and 64-5. The select gates 62 and 66 are separated from the adjacent word lines 64-1 and 64-5 by a spacing, s1, of approximately 0.35 micron. The word lines 64-1 through 64-5 are separated by a spacing, s2, of approximately 0.25 micron.
Although the conventional method 10 can be used to form select gates 62 and 66 as well as word lines 64-1, 64-2, 64-3, 64-4 and 64-5, one of ordinary skill in the art will readily recognize that optical effects adversely affect the performance of the conventional memory device 40xe2x80x2. Referring to FIGS. 2B and 2C, the conventional lines 52 and 56 have a width, w1, corresponding to the width set by the conventional mask 30 and that is desired for the select gates. The conventional lines 54-2, 54-3 and 54-4 have a width w2 corresponding to the width in the conventional mask 30. Similarly, the conventional lines 54-2, 54-3 and 54-4 are spaced by a distance s2 corresponding to the spacing set by the conventional mask 30. The width of the conventional lines 54-1 and 54-5, however, is affected by the greater distance between the polygons 32 and 34-1 and the polygons 36 and 34-5, respectively. In particular, it is known that optical effects cause structures which are in closer proximity to be printed with a smaller width than structures that are separated by a larger distance. Thus the lines 54-1 and 54-5 are printed with a larger width, w3, than the lines 54-2, 54-3 and 54-4 because a greater distance separates the lines 54-1 and 54-5 from the lines 52 and 56, respectively.
Because the widths of the lines 54-1 and 54-5 are different from the widths of the lines 54-2, 54-3 and 54-4, the widths of word lines 64-1 and 64-5 are different from the widths of word lines 54-2, 54-3 and 54-4. This is depicted in FIG. 2C, which indicates that the word lines 64-1 and 64-5 have a width of w3 while the word lines 64-2, 64-3 and 64-4 have a width of w2. Because the word lines 64-1 and 64-5 have a different width from the remaining word lines 64-2, 64-3 and 64-4, the word lines 64-1 and 64-5 have a different electrical characteristics. Thus, the performance of word lines 64-1 and 64-5 differs from that of word lines 64-2, 64-3 and 64-4. Different performances for different word lines cause differences in the behavior of memory cells in the conventional memory device 40xe2x80x2. Differences in behavior of the memory cells of the conventional memory device 40xe2x80x2 is undesirable.
Accordingly, what is needed is a system and method for providing lines having similar characteristics. The present invention addresses such a need.
The present invention provides a method and system for providing a plurality of lines in a semiconductor memory device. The method and system comprise providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.
According to the system and method disclosed herein, the present invention provides lines which have substantially the same width and, therefore, substantially the same performance.